Flash memory cells are used in connection with a variety of modern technologies such as programmable logic devices, standalone memory cards and drives, embedded systems, and other products. As is well known, flash memory cells generally provide the advantage of maintaining non-volatile storage of programmed data for extended periods of time.
Before flash memory cells can be programmed, however, they normally must be erased to ensure that individual flash memory cells are not left in a programmed state with bit values that are no longer valid. Such erasures are typically performed on entire blocks of flash memory containing many individual flash memory cells. After a block of flash memory has been erased, the state of individual flash memory cells must be checked to confirm that each flash memory cell is in an erased state. If this verification process is not performed, unerased preprogrammed bits may introduce errors in future programming of the flash memory.
In conventional flash memory implementations, the erasure of each flash memory cell is determined in a “bit-by-bit” fashion by consecutively reading the state of the individual flash memory cells. Unfortunately, such conventional flash memory implementations can require a large amount of time to verify the erasure of every individual flash memory cell in a given flash memory block. Such bit-by-bit processes can become especially time-consuming for modern devices employing large numbers of flash memory cells. As a result, there is a need for an improved approach to erase verification of flash memory cells that reduces the performance-limiting delays associated with existing bit-by-bit approaches.